{
 "isa": "RX16",
 "isa_revision": "r26",
 "mode": "standard",
 "word_bits": 16,
 "instr_bits": 16,
 "num_regs": 8,
 "mem_words": 256,
 "graded_mem_window": 64,
 "max_steps": 4096,
 "memory_model": "16-bit word-addressed; address arithmetic mod mem_words",
 "registers": {
  "count": 8,
  "width_bits": 16,
  "field_bits": 3,
  "note": "A 3-bit register field value v denotes architectural register R[field_to_reg[v]].",
  "field_to_reg": [
   6,
   3,
   1,
   7,
   4,
   2,
   5,
   0
  ]
 },
 "flags": {
  "names": [
   "Z",
   "N",
   "C",
   "V"
  ],
  "status_nibble_order": [
   "N",
   "Z",
   "C",
   "V"
  ],
  "initial_value": "taken from the program's flags0 field; NOT implicitly zero -- load flags0 as part of the starting state",
  "Z": "set iff (result & 0xFFFF) == 0",
  "N": "bit 15 of the 16-bit result",
  "C": "ADD: carry-out of bit 15; SUB/CMP: NOT borrow (i.e. set iff Rn>=Rm unsigned); SHL/SHR: last bit shifted out (0 if shamt==0)",
  "V": "signed overflow of ADD/SUB"
 },
 "opcodes": {
  "ADD": 5,
  "SUB": 6,
  "AND": 18,
  "OR": 10,
  "XOR": 16,
  "MOV": 3,
  "CMP": 4,
  "TST": 7,
  "ADDI": 8,
  "SHL": 2,
  "SHR": 11,
  "MVI": 17,
  "LD": 1,
  "ST": 13,
  "LDM": 0,
  "STM": 9,
  "BR": 15,
  "JR": 12,
  "HLT": 14
 },
 "opcode_field_bits": 5,
 "predication": {
  "predicated_formats": [
   "br",
   "jr",
   "ri",
   "rs"
  ],
  "unconditional_formats": [
   "rr",
   "wi",
   "mem",
   "mreg",
   "none"
  ],
  "rule": "Predicated instructions (forms ri, rs, br, jr) carry a 3-bit predicate (a condition code) in slot A. If it is FALSE the instruction is SKIPPED ENTIRELY: no register write, no branch, and -- CRITICALLY -- NO FLAG UPDATE. BR's predicate IS its branch condition. The rr/wi/mem/mreg forms are unconditional (always execute)."
 },
 "immediates": {
  "ri_bits": 5,
  "ri_signed": true,
  "shamt_bits": 4,
  "shamt_signed": false,
  "memoff_bits": 4,
  "memoff_signed": true,
  "wimm_bits": 8,
  "wimm_signed": true,
  "broff_bits": 6,
  "broff_signed": true,
  "broff_unit": "words; byte target offset is 2*broff"
 },
 "conditions": {
  "field_bits": 3,
  "field_to_cond": [
   "NE",
   "LT",
   "CS",
   "GE",
   "CC",
   "MI",
   "EQ",
   "AL"
  ],
  "semantics": {
   "AL": "always",
   "EQ": "Z==1",
   "NE": "Z==0",
   "LT": "signed N!=V",
   "GE": "signed N==V",
   "CS": "C==1",
   "CC": "C==0",
   "MI": "N==1"
  }
 },
 "semantics_toggles": {
  "branch_base": "next",
  "branch_base_note": "BR: PC <- PC_base + 2*sx(broff) when taken, where PC_base is the branch's OWN byte-address if 'self', else the next instruction's address (own+2) if 'next'.",
  "ldm_dir": "asc",
  "ldm_writeback": false,
  "ldm_note": "LDM/STM: registers in the reglist are transferred in ASCENDING architectural register number (R0..R7), one word each, beginning at address = R[Rn]. After each transfer the working address moves +1 word (ldm_dir=='asc') or -1 word (=='desc'), modulo mem_words. If ldm_writeback, the final working address is written back to R[Rn] AFTER all transfers (note: if Rn is also in the reglist, the transfer uses its pre-writeback value)."
 },
 "instruction_set": {
  "ADD": {
   "form": "rr",
   "writes_reg": true,
   "updates_flags": "ZNCV",
   "semantics": "Rd <- Rn + Rm; set Z,N,C,V"
  },
  "SUB": {
   "form": "rr",
   "writes_reg": true,
   "updates_flags": "ZNCV",
   "semantics": "Rd <- Rn - Rm; set Z,N,C,V"
  },
  "AND": {
   "form": "rr",
   "writes_reg": true,
   "updates_flags": "ZN",
   "semantics": "Rd <- Rn & Rm; set Z,N (C,V unchanged)"
  },
  "OR": {
   "form": "rr",
   "writes_reg": true,
   "updates_flags": "ZN",
   "semantics": "Rd <- Rn | Rm; set Z,N (C,V unchanged)"
  },
  "XOR": {
   "form": "rr",
   "writes_reg": true,
   "updates_flags": "ZN",
   "semantics": "Rd <- Rn ^ Rm; set Z,N (C,V unchanged)"
  },
  "MOV": {
   "form": "rr",
   "writes_reg": true,
   "updates_flags": "none",
   "semantics": "Rd <- Rn (Rm ignored); no flags"
  },
  "CMP": {
   "form": "rr",
   "writes_reg": false,
   "updates_flags": "ZNCV",
   "semantics": "compute Rn - Rm; set Z,N,C,V; write NO register"
  },
  "TST": {
   "form": "rr",
   "writes_reg": false,
   "updates_flags": "ZN",
   "semantics": "compute Rn & Rm; set Z,N; write NO register"
  },
  "ADDI": {
   "form": "ri",
   "writes_reg": true,
   "updates_flags": "ZNCV",
   "semantics": "Rd <- Rd + sx(imm) [2-operand]; set Z,N,C,V"
  },
  "SHL": {
   "form": "rs",
   "writes_reg": true,
   "updates_flags": "ZNC",
   "semantics": "Rd <- Rd << zx(shamt) [2-operand]; C <- last bit shifted out (0 if shamt==0); set Z,N"
  },
  "SHR": {
   "form": "rs",
   "writes_reg": true,
   "updates_flags": "ZNC",
   "semantics": "Rd <- Rd >> zx(shamt) logical [2-operand]; C <- last bit shifted out (0 if shamt==0); set Z,N"
  },
  "MVI": {
   "form": "wi",
   "writes_reg": true,
   "updates_flags": "none",
   "semantics": "Rd <- sx(imm); no flags"
  },
  "LD": {
   "form": "mem",
   "writes_reg": true,
   "updates_flags": "none",
   "semantics": "Rd <- M[(Rn + sx(off)) mod mem_words]; no flags"
  },
  "ST": {
   "form": "mem",
   "writes_reg": false,
   "updates_flags": "none",
   "semantics": "M[(Rn + sx(off)) mod mem_words] <- Rd; no flags"
  },
  "LDM": {
   "form": "mreg",
   "writes_reg": true,
   "updates_flags": "none",
   "semantics": "load-multiple (see semantics_toggles.ldm_note); no flags"
  },
  "STM": {
   "form": "mreg",
   "writes_reg": false,
   "updates_flags": "none",
   "semantics": "store-multiple (see semantics_toggles.ldm_note); no flags"
  },
  "BR": {
   "form": "br",
   "writes_reg": false,
   "updates_flags": "none",
   "semantics": "if cond holds: PC <- branch_base + 2*sx(off) (see semantics_toggles.branch_base_note)"
  },
  "JR": {
   "form": "jr",
   "writes_reg": false,
   "updates_flags": "none",
   "semantics": "if predicate holds: PC <- R[Rn] (absolute)"
  },
  "HLT": {
   "form": "none",
   "writes_reg": false,
   "updates_flags": "none",
   "semantics": "stop execution"
  }
 },
 "encoding": {
  "bit_order_msb": 15,
  "word": "(opcode<<11) | format-bits; immediate/reglist fields right-justified at bit 0",
  "opcode_field": {
   "hi": 15,
   "lo": 11
  },
  "slots": {
   "A": {
    "hi": 10,
    "lo": 8
   },
   "B": {
    "hi": 7,
    "lo": 5
   },
   "C": {
    "hi": 4,
    "lo": 2
   }
  },
  "rr": {
   "Rm": "A",
   "Rd": "B",
   "Rn": "C",
   "predicated": false,
   "note": "register-register; CMP/TST use Rn(C) and Rm(A), write no register"
  },
  "ri": {
   "pred": "A",
   "Rd": "B",
   "imm": "bits[ri_bits-1:0], sign-extended; Rd<-Rd+imm",
   "predicated": true
  },
  "rs": {
   "pred": "A",
   "Rd": "B",
   "shamt": "bits[shamt_bits-1:0], ZERO-extended; Rd<-Rd shifted",
   "predicated": true
  },
  "wi": {
   "Rd": "A",
   "imm": "bits[wimm_bits-1:0], sign-extended",
   "predicated": false
  },
  "mem": {
   "Rn": "A",
   "Rd": "B",
   "off": "bits[memoff_bits-1:0], sign-extended; addr=Rn+off",
   "predicated": false
  },
  "mreg": {
   "Rn": "A",
   "reglist": "bits[7:0], 8-bit register mask (bit r => Rr)",
   "predicated": false
  },
  "br": {
   "cond": "A",
   "off": "bits[broff_bits-1:0], sign-extended, in words",
   "predicated": true,
   "note": "the cond field IS the branch predicate"
  },
  "jr": {
   "pred": "A",
   "Rn": "B",
   "predicated": true
  },
  "none": {
   "predicated": false
  }
 },
 "execution_model": "PC is a byte address; instructions are 16 bits = 2 bytes; PC starts at 0 and advances by 2 unless a taken branch/jump changes it. Code memory is the program word array (word i lives at byte address 2*i). Execution stops at HLT, when PC leaves [0, 2*code_len), or after max_steps=4096 instructions (quiescence). INITIAL ARCHITECTURAL STATE: each program publishes its full starting state -- regs0 (R0..R7), mem0 (the data memory) and flags0 (the initial Z/N/C/V). Load all three before executing; flags0 is NOT assumed to be zero, and a predicated instruction reached before any flag-setting instruction reads it.",
 "limits": {
  "num_programs": 24,
  "prog_len": [
   12,
   28
  ],
  "predication_rate": 0.3,
  "mutation": "base"
 }
}