STEP 000 | START | STATE=00000000 00000000 00000000 00000000
STEP 001 | BIT=02 | CHANGE=0->1 | STATE=01000000 00000000 00000000 00000000 | BASIS=Visible generator logic requires S2=true; partial pattern remains disabled
STEP 002 | BIT=04 | CHANGE=0->1 | STATE=01010000 00000000 00000000 00000000 | BASIS=Visible generator logic requires S4=true; partial pattern remains disabled
STEP 003 | BIT=05 | CHANGE=0->1 | STATE=01011000 00000000 00000000 00000000 | BASIS=Visible generator logic requires S5=true; partial pattern remains disabled
STEP 004 | BIT=07 | CHANGE=0->1 | STATE=01011010 00000000 00000000 00000000 | BASIS=Completed visible 01011010 interlock pattern; only then generator is enabled